Module mpc_engine::circuit
source · Expand description
The Circuit representation used by the MPC engine.
A circuit is made up of logic gates and value-carrying wires between the gates. Each gate takes one or more wires as input, depending on the type of gate, and has exactly one output wire.
Conceptually, a circuit is a sequence of input or logic (XOR/AND/NOT) gates,
with all input gates at the beginning of the sequence, followed by all logic
gates. The index of a gate in the sequence determines its “wire index”,
which is available as the input to any gate later in the sequence. For
example, in a circuit with two input gates (1 bit for party A, 1 bit for
party B), followed by three logic gates (an XOR of the two input gates, an
AND of the two input gates, and an XOR of these two XOR/AND gates), the
input gates would be the wires 0 and 1, the XOR of these two input gates
would be specified as Gate::Xor(0, 1) and have wire index 2, the AND of
the two input gates would be specified as Gate::And(0, 1) and have wire
index 3, and the XOR of the two logic gates would be specified as
Gate::Xor(2, 3) and have wire index 4:
Input A (Wire 0) ----+----------+
| |
Input B (Wire 1) ----|-----+----|-----+
| | | |
+-XOR-+ | |
(Wire 2) =====> | | |
| +-AND-+
(Wire 3) =======|========> |
+---XOR----+
(Wire 4) ==========> |
The input gates of different parties cannot be interleaved: Each party must supply all of their inputs before the next party’s inputs can start.
At least one input bit must be specified, and every party contributing inputs to the circuit has to specify at least one input bit. Party input gates may not refer to other input gates’ wire indices.
This module is derived from the circuit representation of
garble_lang, the
license of which is reproduced below.
MIT License
Copyright (c) 2022 SINE e.V.
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Structs§
- Representation of a circuit evaluated by an MPC engine.
Enums§
- Errors occurring during the validation or the execution of the MPC protocol.
- An input gate or a logic gate with its input wire specification.
Type Aliases§
- Specifies how many input bits a party is expected to contribute to the evaluation.
- Data type to uniquely identify gate output wires.